Neutron induced single event upset (SEU) testing of commercial memory devices with embedded error correction codes (ECC)

Abstract

Results of neutron induced single event upset testing of devices with embedded error correction codes are described. Specifically, Cypress CY7C1061GE30-10BVXI and CY7C1061GE-10BVXI 16-Mbit Static Random Access Memories (SRAMs), and a memory system, consisting of a Tundra Tsi107 PowerPC Host Bridge interfacing with nine Micron MT48LC32M8A2TG-75ITD 256-Mbit Synchronous Dynamic Random Access Memories (SDRAMs). Four samples of each memory system or device type were irradiated with a 14-MeV neutron source. The units were irradiated using a continual read/write correct loop using several bit patterns. Results for both correctable and uncorrectable errors are presented along with cross section data and soft error rates.