T. Toifl, M. Braendli, A. Cevrero, P. Francese, M. Kossel, L. Kull, D. Luu, C. Menolfi, T. Morf, Ilter Özkaya, Hazar Yueksel
{"title":"Design considerations for 50G+ backplane links","authors":"T. Toifl, M. Braendli, A. Cevrero, P. Francese, M. Kossel, L. Kull, D. Luu, C. Menolfi, T. Morf, Ilter Özkaya, Hazar Yueksel","doi":"10.1109/ESSCIRC.2016.7598345","DOIUrl":null,"url":null,"abstract":"The constantly increasing need for I/O bandwidth push electrical backplane links to data rates of 50Gb/s and above. Although board materials have improved significantly, backplane links are increasingly limited by signal attenuation while suffering from ISI, jitter, device noise and cross-talk. In this paper we summarize these limitations, and show possible directions to cope with them in order to further extend the achievable data rate.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2016.7598345","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
The constantly increasing need for I/O bandwidth push electrical backplane links to data rates of 50Gb/s and above. Although board materials have improved significantly, backplane links are increasingly limited by signal attenuation while suffering from ISI, jitter, device noise and cross-talk. In this paper we summarize these limitations, and show possible directions to cope with them in order to further extend the achievable data rate.
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