A new user-friendly ATPG platform for digital circuits

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2016-04-20 DOI:10.1109/DDECS.2016.7482474

Marek Lipovský, Ján Svarc, E. Gramatová, P. Fiser

引用次数: 1

Abstract

The paper presents a new graphical platform for automatic test patterns generation and fault simulation for digital circuits. The platform integrates two existing academic tools for test pattern generation and fault simulation: ATALANTA and HOPE. Both tools use a specific format "bench" for circuit description which is not suitable in connection to professional CAD tools. Therefore, the platform has been extended by a new translator for mapping a VHDL digital circuit model to the format "bench". The platform contains also a separate random test patterns generator linked to the fault simulator HOPE and generation of test pairs for delay faults using the transition fault model. The new automatic test pattern generation platform provides a user-friendly environment suitable for education.

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一个新的用户友好的数字电路ATPG平台

提出了一种用于数字电路自动测试图生成和故障仿真的图形化平台。该平台集成了两种现有的用于测试模式生成和故障仿真的学术工具:atlanta和HOPE。这两种工具都使用特定格式的“工作台”进行电路描述，这与专业CAD工具的连接不合适。因此，该平台通过一个新的转换器进行了扩展，用于将VHDL数字电路模型映射到“bench”格式。该平台还包含一个独立的随机测试模式生成器，与故障模拟器HOPE相连，并使用转换故障模型生成延迟故障的测试对。新的自动测试模式生成平台提供了一个适合教育的用户友好的环境。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

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