Line Edge Roughness due to Oxide Rie Process : Topic: AM

M. Steigerwalt, David Urrabazo, R. Baiocco, Ryan Kelly, A. Minns, Derek Dechamplain, Qifang Qiao, R. van Roijen
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Abstract

The performance of a subset of the logic devices on a recent new design showed unexpected variation. Analysis showed that the nitride/oxide spacer exhibited excessive roughness in certain areas of a logic chip, causing the observed device shift. To execute the experiments required to correct the issue we developed a method to use inline measurement to quantify spacer quality. This helped to improve spacer quality without delaying availability of the product.
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氧化Rie工艺引起的线边缘粗糙度:主题:AM
在最近的新设计中,逻辑器件子集的性能出现了意想不到的变化。分析表明,氮化物/氧化物间隔层在逻辑芯片的某些区域表现出过度的粗糙度,导致观察到的器件移位。为了执行纠正该问题所需的实验,我们开发了一种使用在线测量来量化隔离器质量的方法。这有助于在不延迟产品可用性的情况下提高垫片质量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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