Low Power and High Speed Designs of CIC Filter for Sigma-Delta ADCs

Abstract

Cascaded integrator-comb (CIC) filter is widely used as the first stage of decimation filter in Sigma-Delta ADC due to its simple structure and high operation frequency. This paper mainly consists of two works. First, aiming at the power consumption bottleneck, an improved hybrid CIC filter with 625MHz working frequency, 3bits input, 4-level cascade and extraction multiple of 8 is designed in 28nm CMOS. Second, aiming at the speed limitation, a non-recursive CIC filter with 2GHz operating frequency, 3bits input, 4-level cascade and 8 extraction multiple is optimized by extraction multiple allocation strategy in 28nm CMOS. The results of placement and routing (PR) show that under the same frequency, the 0.2607mW power of the hybrid structure CIC filter is reduced by 41.69% compared with traditional recursive structure, and its area is increased by 10.8%. The non-recursive CIC filter can reach 2GHz frequency, with power consumption of 0.9493mW. Compared with the traditional recursive structure, the speed is increased by 3.2 times, and the area is increased by 5.33%.