Logic Diagnosis and Yield Learning

Abstract

Summary form only given. In the past, logic diagnosis was primarily used to support failure analysis labs. It was typically done on a small sample of defective chips, therefore long processing times, manual generation of diagnostic patterns, and usage of expensive equipment was acceptable. In addition to failure analysis, yield learning relied on test chips and in-line inspection. Recently, sub-wavelength lithography processes have started introducing new yield loss mechanisms at a rate, magnitude, and complexity large enough to demand major changes in the process. Test chips are no longer able to represent the various failure mechanisms originating from critical features. The number of such features is too large to properly represent it on silicon in a cost-effective manner. For new processes it is also impossible to predict all significant features up front. With the decreasing sizes of defects and increasing percentage of invisible ones, in-line inspection data is not always available.