Design of a 100 MHz hybrid number system data execution unit

Abstract

A hybrid number system data execution unit which supports the 32-b IEEE 754 floating-point and a 32-b logarithmic number system is described. By using the proposed conversion algorithms, a very-high-performance data execution unit is realized for all basic arithmetic operations, such as multiplication, division, squaring, and square root. These operations, in a pipelined structure, can be executed in 10 ns in a 0.8-μm CMOS technology. Critical paths, such as the required 12-b by 12-b Booth multiplier, are implemented with the redundant binary bit representation to enhance the performance, and the multiple-port ROMs are carefully laid out and use half-VDD precharge to reduce the access time. The architecture, circuit design, and design methodology are described in detail. Simulated circuit performance of this data execution unit is also discussed