Compliant probe substrates for testing high pin-count chip scale packages

Abstract

The ultra high I/O density sea of leads (SoL) chip-scale package (Bakir et al, Proc. 52nd Electron. and Comp. Tech. Conf., 2002) has the potential to revolutionize testability of a gigascale system-on-a-chip (SoC). With this wafer-level packaging technology, testing and burn-in can be migrated to the wafer-level. The parallel nature of wafer-level testing and burn-in, facilitated by SoL, can drive down the cost of obtaining a packaged known good die. The extremely high I/O density of the SoL package, typically 12,000 I/O/cm/sup 2/, provides access to internal nodes on a chip. Greater node access enables partitioning of the device-under-test (DUT) into smaller units while maintaining the ability to control and observe them. In turn, smaller units for testing equates to reduced test vector sets and shorter test times - a much sought after objective. A compliant probe technology has been developed to contact the SoL package. It provides a high-density, low-parasitic, and reliable interface between the package and automated test equipment (ATE) during testing. The compliant probes when used jointly with SoL offer a novel approach to efficiently testing a future SoC.