Y. Sasago, H. Kurata, T. Arigane, K. Otsuga, T. Kobayashi, Y. Ikeda, T. Fukumura, S. Narumi, A. Sato, T. Terauchi, M. Shimizu, S. Noda, K. Kozakai, O. Tsuchiya, K. Furusawa
{"title":"90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F/sup 2//bit and programming throughput of 10 MB/s","authors":"Y. Sasago, H. Kurata, T. Arigane, K. Otsuga, T. Kobayashi, Y. Ikeda, T. Fukumura, S. Narumi, A. Sato, T. Terauchi, M. Shimizu, S. Noda, K. Kozakai, O. Tsuchiya, K. Furusawa","doi":"10.1109/IEDM.2003.1269406","DOIUrl":null,"url":null,"abstract":"The first true 2-F/sup 2//bit flash cell with a programming throughput of 10 MB/s was developed. In this cell, diffusion-layer local bit lines of an assist-gate AND-type flash are replaced by inversion-layer ones under assist gates. The bit-line pitch is thus reduced to 2 F. A drain-disturbance-free and soft-write-free flash cell was produced by means of a new diffusion-layer-less technology. Source-side injection programming is applicable to the new flash cell; therefore, the cell programming time is reduced to 1 /spl mu/s. The smallest memory cell (0.0162 /spl mu/m/sup 2//bit) achieved to date was accomplished by using a 90-nm technology node and applying multi-level cell technology.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Electron Devices Meeting 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2003.1269406","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
The first true 2-F/sup 2//bit flash cell with a programming throughput of 10 MB/s was developed. In this cell, diffusion-layer local bit lines of an assist-gate AND-type flash are replaced by inversion-layer ones under assist gates. The bit-line pitch is thus reduced to 2 F. A drain-disturbance-free and soft-write-free flash cell was produced by means of a new diffusion-layer-less technology. Source-side injection programming is applicable to the new flash cell; therefore, the cell programming time is reduced to 1 /spl mu/s. The smallest memory cell (0.0162 /spl mu/m/sup 2//bit) achieved to date was accomplished by using a 90-nm technology node and applying multi-level cell technology.