Accelerated Active Life Test of GaAs FET and a New Failure Mode

Abstract

An initial study at Avantek has established that static accelerated life tests on GaAs FET devices predict about an order of magnitude longer life than active accelerated life tests (tests at elevated temperatures with normal operating bias applied). In order to obtain reliable data, it is necessary to ensure that the devices do not oscillate while under test. To avoid oscillations the drain and source of the FET must be terminated in impedances which are controlled from DC to Fmax. For many of the devices tested Fmas was as high as 80 GHz. A test fixture with 50-ohm ceramic microstrip lines connected to the source and drain proved successful. The packaged GaAs FET and one end of each ceramic microstrip line was attached to a temperature-controlled heated stage. The GaAs FETs used in these tests were fabricated with AuGe/Ni/Au ohmic contacts and TiW/Au overlay metal. An identical layer of TiW/Au was also used for the Schottky barrier gate. They were then her-metically sealed in metal ceramic packages. The failure criterion used to define end of life was a 1-dB degradation of S21 (insertion gain in 50-ohm system) measured at 6 GHz. Insertion gain, S21 was measured with bias conditions which were typically optimum for low noise so long as this current was below Idss. If after stress, Idss was below the current which was previously optimum for noise figure, then measurements would be made at Idss. The average activation energy of the Arrhenius curve of this failure mode was 1.