K. Sakaue, Y. Shobatake, M. Motoyama, Y. Kumaki, S. Takatsuka, S. Tanaka, H. Hara, K. Matsuda, S. Kitaoka, M. Noda, Y. Niitsu, M. Norishima, H. Momose, K. Maeguchi, S. Shimizu, T. Kodama
{"title":"A 0.8 μm BiCMOS ATM switch on the 800 Mbps asynchronous buffered banyan network","authors":"K. Sakaue, Y. Shobatake, M. Motoyama, Y. Kumaki, S. Takatsuka, S. Tanaka, H. Hara, K. Matsuda, S. Kitaoka, M. Noda, Y. Niitsu, M. Norishima, H. Momose, K. Maeguchi, S. Shimizu, T. Kodama","doi":"10.1109/VLSIC.1990.111097","DOIUrl":null,"url":null,"abstract":"A two-input, two-output element switch for use in future ATM (asynchronous transfer mode) switching systems for buffered banyan networks with CASO (contents associated output) buffers has been realized in 0.8-μm BiCMOS technology. Three key features of the element switch architecture are CASO buffers to increase the throughput, SCDB (synchronization in clocked dual-port buffer) to make asynchronous cell transmission possible on the element switches with a simple structure, and CELL-BYPASS, which lowers the latency (the time of cell passage through the element switch). The element switch adopted an ECL (emitter coupled logic) interface to achieve high through rate. Using these techniques, a high-speed, low-latency, very-large-scale buffered self-routing switching network is easily constructed","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1990.111097","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A two-input, two-output element switch for use in future ATM (asynchronous transfer mode) switching systems for buffered banyan networks with CASO (contents associated output) buffers has been realized in 0.8-μm BiCMOS technology. Three key features of the element switch architecture are CASO buffers to increase the throughput, SCDB (synchronization in clocked dual-port buffer) to make asynchronous cell transmission possible on the element switches with a simple structure, and CELL-BYPASS, which lowers the latency (the time of cell passage through the element switch). The element switch adopted an ECL (emitter coupled logic) interface to achieve high through rate. Using these techniques, a high-speed, low-latency, very-large-scale buffered self-routing switching network is easily constructed