Extending an FET layout verification system to bipolar technology

J. Gannett
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引用次数: 4

Abstract

Rink, an automatic layout verification system intended for FET technologies, has been enhanced to handle bipolar designs. A straightforward procedure that uses Rink's parasitic capacitance extractor to solve the bipolar device identification problem is described. The bipolar enhancements to Rink have been used successfully on a set of seven high-speed bipolar chips designed for lightwave communication. These chips ranged in complexity from 23 to 67 devices. Full-custom, nonmanhattan layouts for these chips were created on polygon-pusher style layout editors. For each chip, Rink executed an automatic comparison of the netlist extracted from the layout against a SPICE reference netlist. The latter has been coded for SPICE design simulations. Several fatal connectivity errors were uncovered as were a few significant disparities in resistor values and transistor sizes.<>
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将场效应管布局验证系统扩展到双极技术
Rink是一个用于FET技术的自动布局验证系统,已经增强到可以处理双极设计。一个简单的程序,使用Rink的寄生电容提取器来解决双极器件识别问题。Rink的双极增强技术已成功应用于一组用于光波通信的7个高速双极芯片上。这些芯片的复杂程度从23到67个设备不等。这些芯片的全定制,非曼哈顿布局是在多边形推手式布局编辑器上创建的。对于每个芯片,Rink将从布局中提取的网表与SPICE参考网表进行自动比较。后者已被编码用于SPICE设计仿真。发现了几个致命的连接错误,以及电阻值和晶体管尺寸的一些显着差异
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The best-case power-delay products for polysilicon-contacted bipolar-transistor gates. A theoretical study The effect of emitter sidewall isolation on the emitter junction in a double layer polysilicon bipolar process Delay analysis for BiCMOS drivers Comparing techniques for fabrication polysilicon contacted emitter bipolar transistors Thin base formation by double diffused polysilicon technology
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