J. Yuan, V. Chan, M. Eller, N. Rovedo, H.K. Lee, Y. Gao, V. Sardesai, N. Kanike, V. Vidya, O. Kwon, O. Kwon, J. Yan, S. Fang, W. Wille, H. Wang, Y. Chow, R. Booth, T. Kebede, W. Clark, H. Mo, C. Ryou, J. Liang, J. Yang, C.W. Lai, S.S. Naragad, O. Gluschenkov, M. Visokay, C. Radens, S. Deshpande, H. Shang, Y. Li, N. Cave, J. Sudijono, J. Ku, R. Divakaruni
{"title":"A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate","authors":"J. Yuan, V. Chan, M. Eller, N. Rovedo, H.K. Lee, Y. Gao, V. Sardesai, N. Kanike, V. Vidya, O. Kwon, O. Kwon, J. Yan, S. Fang, W. Wille, H. Wang, Y. Chow, R. Booth, T. Kebede, W. Clark, H. Mo, C. Ryou, J. Liang, J. Yang, C.W. Lai, S.S. Naragad, O. Gluschenkov, M. Visokay, C. Radens, S. Deshpande, H. Shang, Y. Li, N. Cave, J. Sudijono, J. Ku, R. Divakaruni","doi":"10.1109/ICSICT.2008.4734744","DOIUrl":null,"url":null,"abstract":"This paper presents a cost-effective low power 45 nm bulk technology platform, primarily designed to serve the wireless multimedia and consumer electronics need. This technology platform features carbon co-IIP in the nMOS halo, laser annealing scheme, stress liner on the 45°-rotated wafer (<100>) for process simplicity to achieve high device performance and low leakage together. Drive current as high as 650/320 uA/um at Ioff of 0.5 nA/um with Vdd=1.1V has been achieved for both NMOS and PMOS respectively. Ring oscillator speed (FO=1) has been boosted up by 30% with the device optimization. SRAM Vt mismatch is also improved by 10% with carbon co-IIP with good SRAM characteristics and low leakage current in 0.299 um2 cell.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.2008.4734744","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper presents a cost-effective low power 45 nm bulk technology platform, primarily designed to serve the wireless multimedia and consumer electronics need. This technology platform features carbon co-IIP in the nMOS halo, laser annealing scheme, stress liner on the 45°-rotated wafer (<100>) for process simplicity to achieve high device performance and low leakage together. Drive current as high as 650/320 uA/um at Ioff of 0.5 nA/um with Vdd=1.1V has been achieved for both NMOS and PMOS respectively. Ring oscillator speed (FO=1) has been boosted up by 30% with the device optimization. SRAM Vt mismatch is also improved by 10% with carbon co-IIP with good SRAM characteristics and low leakage current in 0.299 um2 cell.