S. Takagi, H. Nitta, M. Furihata, M. Fujii, M. Nagata, T. Yanagisawa
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Abstract
Proposes an implementation of a monolithic filter with a 100 MHz cutoff frequency and a 200 MHz transmission zero. The method is based on the modified leapfrog simulation and requires no floating capacitors. Integrators are realized by balanced-type NICs because the NICs have excellent high frequency characteristics. Results of computer simulation are also presented
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