D. Lin, Xiangyu Wu, D. Cott, D. Verreck, B. Groven, S. Sergeant, Q. Smets, S. Sutar, I. Asselberghs, I. Radu
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引用次数: 13
Abstract
We have engineered dual gate WS2 transistors with scaled top and back gate stacks based on a surface physisorption ALD approach for advanced logic applications. Connected dual gate MOSFET operation with a 2ML WS2 channel reaches 210μA/um drain current and 2.7μF/cm2 capacitance (>3.4×1013/cm2 sheet charge density) at 3V gate bias, with >108 on-off ratio, 120μS/um max. transconductance and 109mV/dec sub-threshold swing at 100nm Lch. This dual gate design enables us to explore EOT scaling, ambipolar I-V and C-V(capacitance-voltage) response on CVD WS2 channel.
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