Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool

Abstract

Traditional synthesis flows dedicated to design ASICs typically adopt standard cells approach to generate VLSI circuits. As a consequence, the layouts of these circuits are not fully optimized due to the restricted number of cells present in the library. To solve this problem, ASTRAN, an open source automatic synthesis tool, was developed. This tool generates layouts with unrestricted cell structures and obtains results with similar density compared to state-of-the-art alternatives. A key step on the ASTRAN flow is the transistor folding, which consists in breaking the transistors that exceed the height limit defined in the project rules. This step is executed in ASTRAN only into single transistors. This paper addresses this issue and introduces a new folding methodology that identifies all stacks of transistors series and applies the folding technique for each of these arrangements. The results obtained through this new folding technique show reductions in cell area.