Package design challenges and optimizations in density efficient (Intel® Xeon® processor D) SoC

Abstract

Xeon®-D[1] brings the high performance of Xeon® processors into a dense, low-power System-on-Chip (SoC). This paper addresses the importance of cost-performance trade off optimization for the Xeon®-D package. It describes how to determine the low cost package factors (size, footprint, pin map and layer count) without compromising the performance of the system. 10GbE signal integrity design and HSD pin map optimization are discussed. Low power architecture and package power delivery features including FIVR are presented in the paper as well.