Hao Ding, Xuqiang Zheng, Danyu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
{"title":"A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS","authors":"Hao Ding, Xuqiang Zheng, Danyu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu","doi":"10.1109/ESSCIRC.2019.8902616","DOIUrl":null,"url":null,"abstract":"This letter presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter with a 2-tap fractional-spaced feed-forward equalizer (FFE) implemented in a 65-nm CMOS process. The tap delay is adjusted by a coarse-fine capacitor array-based delay cell located in the clock path. Dynamic latches, pseudo-AND2s, and bandwidth-enhanced 4:1 MUXs are employed to guarantee an adequate timing margin and a sufficient bandwidth for the 112-Gb/s design. The measurement results show that the fractional-spaced FFE can significantly optimize the eye opening. The fabricated PAM-4 transmitter achieves a maximum data rate of 112 Gb/s with an energy efficiency of 2.17 pJ/bit.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2019.8902616","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This letter presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter with a 2-tap fractional-spaced feed-forward equalizer (FFE) implemented in a 65-nm CMOS process. The tap delay is adjusted by a coarse-fine capacitor array-based delay cell located in the clock path. Dynamic latches, pseudo-AND2s, and bandwidth-enhanced 4:1 MUXs are employed to guarantee an adequate timing margin and a sufficient bandwidth for the 112-Gb/s design. The measurement results show that the fractional-spaced FFE can significantly optimize the eye opening. The fabricated PAM-4 transmitter achieves a maximum data rate of 112 Gb/s with an energy efficiency of 2.17 pJ/bit.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
