A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS

Abstract

This paper presents a 50-Gb/s optical receiver chipset in 45-nm silicon-on-insulator (SOI) CMOS. It comprises a trans-impedance amplifier (TIA) cascaded by a clock and data recovery circuits (CDR). Inverter-based topology with hybrid-peaking inductors is designed to improve the TIA bandwidth (BW). Phase-interpolator-based digital CDR with a baud-rate sampling phase detector is developed for multi-channel integration and low power consumption. Measurements show that the TIA achieves a 53-dBΩ gain and a 27-GHz BW of S21. The receiver prototype outputs a 3.125-GHz recovered clock with −125.84-dBc/Hz@10MHz phase noise and 6.25-Gb/s deserialized data with a 3.5-ps RMS jitter.