H. Kotani, H. Akarnatsu, J. Matsushima, S. Okada, T. Shiragasawa, J. Houma, T. Yamada, M. Inoue
{"title":"A 50MHz 8Mb video RAM with a column direction drive sense amplifier","authors":"H. Kotani, H. Akarnatsu, J. Matsushima, S. Okada, T. Shiragasawa, J. Houma, T. Yamada, M. Inoue","doi":"10.1109/VLSIC.1989.1037511","DOIUrl":null,"url":null,"abstract":"Ahstract-An 8-Mbit (1 Mwordsx8 bits) dynamic RAM for video applications has been developed. To obtain low peak current, a new sensing scheme called the column direction drive (CDD) sense amplifier is proposed. The power supply peak current is reduced to about one fourth when compared with conventional circuits. The chip is able to operate at 50 MHz. The chip is fabricated with a 0.7-pm n-well CMOS, double-level polysilicon, single polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell (SCC) structure. The cell sue is 1.8X3.0 pd, and the chip area is 12.7X 16.91 md.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1989 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1989.1037511","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Ahstract-An 8-Mbit (1 Mwordsx8 bits) dynamic RAM for video applications has been developed. To obtain low peak current, a new sensing scheme called the column direction drive (CDD) sense amplifier is proposed. The power supply peak current is reduced to about one fourth when compared with conventional circuits. The chip is able to operate at 50 MHz. The chip is fabricated with a 0.7-pm n-well CMOS, double-level polysilicon, single polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell (SCC) structure. The cell sue is 1.8X3.0 pd, and the chip area is 12.7X 16.91 md.
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