Intrinsic Capacitance Extraction from Pulsed S-parameters

Abstract

This paper describes a simple approach to dispersion modelling in GaN transistor devices. This technique accounts for the effects of trap-related dispersion on the dynamic nonlinearities i.e. the gate capacitances, in addition to the well-known dispersion of the drain-source current. Using pulsed-bias S-parameters, capacitance surfaces are extracted across the pulsed-IV plane, with the 2D capacitance surface parametrised by the quiescent bias point. Filter networks allow the model to dynamically determine the quiescent bias, ensuring the correct capacitance surface is used according to the slowly-changing state dynamics. This technique provides a model that is capable of producing two distinct sets of S-parameters, depending on whether dc or pulsed biasing is used. The modelling approach is verified up to 40 GHz on a GaN HEMT device, pulsing across the bias plane. Results show good prediction of both the dc and pulsed S-parameter measurements, from a single global model. The importance of extracting elements based on pulsed S-parameter measurements rather than dc S-parameter measurements is made clear through large-signal measurements and simulations.