{"title":"A 7.6 K-gate Josephson macrocell array","authors":"S. Kotani, A. Inoue, S. Hasuo","doi":"10.1109/VLSIC.1990.111099","DOIUrl":null,"url":null,"abstract":"The design and technology for a high-speed Josephson macrocell array are described. A macrocell array including 7.6 k gates was fabricated using a 1.5-μm Nb Josephson process. The chip dimensions are 5×5 mm, and its power consumption is 23 mW. An average gate delay in full adder of 5.3 ps has been achieved using the macrocell","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1990.111099","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The design and technology for a high-speed Josephson macrocell array are described. A macrocell array including 7.6 k gates was fabricated using a 1.5-μm Nb Josephson process. The chip dimensions are 5×5 mm, and its power consumption is 23 mW. An average gate delay in full adder of 5.3 ps has been achieved using the macrocell
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