Challenges in serial protocols Verification on an emulation environment (SATA as an example)

Abstract

System-on-Chip (SoC) Verification is becoming a challenge in nowadays chips. Hardware acceleration is becoming mandatory in SoC verification. Emulation enables longer test cases and more tests to run in less time. However, emulation based verification is still not supporting verification of analog modules. These analog modules are parts of the Physical Layer (PHY) of the Designs-Under-Test (DUT) which includes some digital modules as well to interface with upper layers in the protocol and to control analog modules. So, there is a need to develop emulator friendly physical layers of different protocols to enable emulation based verification. These PHY modules should be flexible enough to cover different configurations of the designs under test. This paper presents how to enable emulation based verification of a full Serial ATA protocol (SATA) controller designs, used in storage applications, using a SATA Verification IP (VIP) and Configurable SATA PHY design.