Process Optimizations for Ge-On-Si Depletion Mode Transistors Using Mesa Architecture

Sumit Choudhary, D. Schwarz, H. Funk, K. P. Sharma, S. Sharma, J. Schulze
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Abstract

The p-Ge layers are epitaxially grown by MBE over the n-Ge and strain-free Ge buffer layers on the Si substrate. The drain-source & channel mesa is patterned in the p-Ge layer to create the raised active channel. Post-plasma oxidation was carried out to improve the interface properties of Ge channel. The proposed process doesn't involve source-drain implants, ease channel patterning using MAPDST, a -ve tone resist with high etch resistance and selectivity w.r.t. Ge. The process flow scheme will utilize the “beyond Si” channel materials over Si substrates, concurrently exploiting the standard well, established state-of-art Si CMOS fabrication technology.
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基于Mesa架构的Ge-On-Si耗尽型晶体管工艺优化
通过MBE在Si衬底上的n-Ge和无应变Ge缓冲层上外延生长p-Ge层。漏源&通道平台在p-Ge层中进行图案化,以创建凸起的有源通道。采用等离子体后氧化技术改善了锗通道的界面性能。所提出的工艺不涉及源漏植入物,使用MAPDST(一种具有高耐蚀性和选择性的- 5色调抗蚀剂)进行通道图形化。该工艺流程方案将利用硅衬底上的“超硅”通道材料,同时利用标准的、成熟的、最先进的硅CMOS制造技术。
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