Fabrication Of 0.06 /spl mu/m Poly-si Gate Using Duv Lithography With A Designed Si/sub x/O/sub y/N/sub z/ Film As An Arc And Hardmask

Abstract

We report fabrication of sub-0.1 pm poly-Si gates using conventional DUV lithography with an optimized Si,O,N, film. This film has dual functions: reducing substrate reflectivit to <1%, and serving as a hardmask for the pol Si etch. &ith an aggressive etch bias process, linewidtxs down to 0.06ym are achieved with good linewidth control ( 3 ~ 1 2 n m ) and a near erfect lineari . Excellent optical manufacturable PECVD deposition process. uniformity of the n a n t k of the AR z is obtained with a Introduction Advances in microlithography have enab!ed si nificant success in VLSI and ULSI technolog While suk0. lpm resist patterning awaits e-beam and %-ray lithography to become widely available, we show that existin DUV using an optimized Si,O,N ARC (anti-reflective coating) and hardmask layer. LPeVD SIN, as an ARC for patterning sub-0.5ym oly gates is reported in 11 and poly reported in [2]. However, these techni ues cannot be used nonuniform gas &strigution causes unacce table optical linewidths 2 0.12pm. DUV or anic ARC has several substrate reflectivity R) and &e infamous undercut resist reduction and etch of the relatively thick ARC layer leaves less resist available to mask the pol Si etch. In contrast, use of Si,O N, results in less resist 7;s~. Moreover, unlike organic ARE, Si,O,N has high selectivity during the polySi overetch. This hardmask roperty is critical in patterning marginal. SixO$J D%6 ARC on metal substrates was initially reported by Ogawa [3], but not used as an etch hardmask. Here we show that an o timized Si,OyN, for reflectance is more severe. Sup ression of substrate obtain sub-0.1 pm poly-Si gates with excelfent CD control. DUV ARC Film Design and Deposition The Si,OyN, refractive indices can be tuned over a wide range by varying its composition. Fig. 1 shows the real and imaginary parts of the refractive index (n and k) as the composition of Si,O N, is tuned by varying the deposition gas flow ratios. ?he Si,OyN, stack is deposited in a commercial P5000 PECVD system. A particle test on 700 wafers shows that there are <20 particles per wafer at size >0.16pm. The Si,O,N, film and backside of wafer is analyzed by TXRF and SIMS: S, C1, K, Ca, Ti, Cr, Fe, Ni, Cu A1 and Zn are at trace level or below detection limit. PECVD provides much better uniformity of n (0=0.19%) and k (0=1.4%) than LPCVD, which is important for ARC implementation. Our methodology to design the thickness and composition of the Si,O,N, ARC starts with Pr0 l i th i2~ simulations to determine the n and k needed for R ~ 1 % at various ARC thicknesses. Fig. 2 plots the simulated contour maps of R at 248nm at thicknesses of 20? 29, 40 nm. We superpose the experimental n vs. k (i.e., Fig.1) on these contours to determine whether at a particular thickness the n and k for R <1% coincide with what can be achieved with our Si,OyN, deposition process. Thus technology may be extended to achieve sub-0.lpm f eatures patterning with etch b a s and organic ARC E or i-line is to pattern sub-0.1 m oly gates. In t R e LPCVD process nonuniformity and biased etch with .i-line K RC achieved disadvantages compared to Si Oy. a,. In addition to higher profile, poor etch se i ectivity to resist during linewidth poly-Si over to ogra h w i ere the resist thicknesses are DUV can be employed to pattern PO P y-Si gates where the reflections and the etch selectivity o P Si,O N, enables us to matching the n and k for low R with reliable deposition conditions we o timize the Si,OyN, composition as n=2.15, k=0.63 and thictness as 29nm. Fig. 3 shows R vs. ARC thickness for this com osition. It indicates a comfortably wide process window (%O*SOA) for the film deposition. Lithogra hy and Etch Figure 4 shows the egect of the DUV ARC film on 0.18pm resist patterning on pol -Si over topography. Notching is completely eliminatei by im lementing the ARC over the poly-Si ate stack. Excelrent dense and isolated profiles of D&V resist over ARC/ oly-Si are >20% and the depth-of-focus is 1.2ym. We have patterned 0.22 to 0.26pm resist lines on polySi over 350nm LOCOS top0 raph using conventional DUV lithography with our AkC d m . To achieve subO.lpm gate length we use a plasma etcher to reduce the patterned resist to sub-0.lpm. During this etch the selectivity of Si,O,N, to resist allows us to optimize the etch for minimum resist loss. Finally a multiple step ARC/ oly-Si etch anisotro ically removes the exposed ost-etch poly-Si gate len ths. Resist linewidths are 0.228.26pm in 0.01 m intervak Using etch bias of 0.16pm, a hearity of sub-0.1 m poly-Si lines with small standard deviation (30=0.01$ is obtained. Fig. 7 shows the sub0.1 pm resist profile after linewidth reduction etch. Fi 8 shows the 0.06pm poly-Si line over a LOCOS to ograpfy. The final gate size which can be achievetis mainly determined by the resist linewidth reduction etch. Remaining resist height is important since it controls whether the poly-Si line is intact after poly etch. The use of Si,O N, is crucial to fabricate 0.06pm poly-Si gate with DUV lithography. Our results show that with or anic ARC 0.08pm is the maximum etch bias possible (Fig.f). Etch of a thick (160nm) organic ARC which does not have ood selectivity removes the resist top surface resulting an 8 not enough resist is left to complete the linewidth reduction etch. The selectivity of Si,OyN, durin the poly-Si overetch further he1 s in maintaining oly Si fines intact where the resist thicLess is margin$ such as for poly-Si over topography. Fig. 9 shows a top-view SEM micro raph of poly-Si lines over LOCOS topography. Broken Enes are observed due to oor resist pattern and low etch selectivity of or anic ARC.%o such roblem is encountered when our S i x O S ARC is used. F!g. 10 shows schematicall the hnewidzth reduction etch processes with Si,OyN A R z and with organic ARC. Si,O,N, serves as both an ARC and a hardmask for the fabrication of sub-0.1 pm poly-Si gate. Conclusions The fabrication of 0.06ym poly-Si gate with conventional DUV lithograph has been successfilly demonstrated using a designed '&,OyN, as DUV ARC and hardmask for linewidth reduction etch techniques. Excellent linearity and small standard deviation for poly gate lengths at sub-0.1 pm range are achieved. Lithography and etch processes implementing the Si,O N, are com ared to that with an organic ARC. It is found That that bo& the optical properties and the etch properties of Si,O N, are critical to achieving the fine poly-Si linewidths. b s e of commercial deposition equipment makes implementation of this process in a manufacturing environment feasible. shown in Fig. 5 . The exposure latitude for 0.2 s pm lines is poly-fi. Fig. 6 summarizes t t: e resist pattern linewidths and oly-Si gates d" own to 0.06pm are obtained. Excellent 131 4-93081 3-75-1 197 1997 Symposium on VLSl Technology Digest of Technical Papers Acknowledgments We thank Chris Bencher for technical discussions and Trace Hurd for metal contamination analysis.