A study of new type CMOS inverter with Gated-IIP load and TFET driver for 22nm technology node

Abstract

This paper presents a new CMOS inverter (CGTFET), which is composed of a Gated control IIP for load transistor (Gated-IIP) and a tunneling field effect transistor (TFET) for driven transistor. Based on the measurement data of Gated-IIP and TFET devices published, we have for the first time drawn the load lines and the quiescent point line (Q line) of the new designed CGTFET compared with the conventional CTFET to verify its feasibility. Additionally, due to our unique structure has simple fabrication process and the output node is shared by the load and the driver, the integration density of our structure can be reduced dramatically. The area benefit thus more than 32.6% has been achieved compared with the conventional CTFET layout. Further, we use Ge Source to further improve NTFET (Q1) driven ability and the performance of the CGTFET.