Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644503
A. Sagara, S. Shibata
Along with the development of the Si semiconductor industry, numerous studies have been carried out on the defects that remain after ion-implantation processes [1]. For example, in the case of high-dose (~1015 cm-2) implantation, dislocation loops can be created even after annealing. These defects are typically evaluated by transmission electron microscopy (TEM) and have been confirmed as a reason for junction leakage [2][3]. Even in low-dose (<; 1013 cm-2) implantation, some intrinsic point defects remain at relatively low annealing temperatures (<; 700 C). These defects have been conventionally analyzed and investigated by optical and electrical characterization techniques, such as photoluminescence (PL) and deep transient level spectroscopy (DLTS) [4]-[6]. In contrast, residual damage in low-dose implanted and high-temperature annealed Si has not been detected and reported. Therefore, it is believed that there is no damage remains in this condition, and, if exists, it has no influence on device performance. Little attention has been paid to the defects that remain after low-dose implantation processes.
{"title":"Thermal behavior of residual damage in low-dose implanted silicon after high-temperature rapid thermal annealing","authors":"A. Sagara, S. Shibata","doi":"10.1109/IWJT.2013.6644503","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644503","url":null,"abstract":"Along with the development of the Si semiconductor industry, numerous studies have been carried out on the defects that remain after ion-implantation processes [1]. For example, in the case of high-dose (~1015 cm-2) implantation, dislocation loops can be created even after annealing. These defects are typically evaluated by transmission electron microscopy (TEM) and have been confirmed as a reason for junction leakage [2][3]. Even in low-dose (<; 1013 cm-2) implantation, some intrinsic point defects remain at relatively low annealing temperatures (<; 700 C). These defects have been conventionally analyzed and investigated by optical and electrical characterization techniques, such as photoluminescence (PL) and deep transient level spectroscopy (DLTS) [4]-[6]. In contrast, residual damage in low-dose implanted and high-temperature annealed Si has not been detected and reported. Therefore, it is believed that there is no damage remains in this condition, and, if exists, it has no influence on device performance. Little attention has been paid to the defects that remain after low-dose implantation processes.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125972966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644517
T. Tomimatsu, T. Yamaguchi, M. Mizuo, T. Yamashita, Y. Kawasaki, A. Ishii
Reduction of leakage current is a grand challenge in logic and analog devices from viewpoints of low power consumption, high resolution, low noise, and so on. As for the P-N junction leakage current, it is reported that the leakage current is caused by several factors such as junction depth [1], shallow trench isolation (STI) stress [2], metal contamination, and crystal defects [3]. In this paper, we focused on the influence of the STI stress on the junction leakage current. To clarify the impact of internal stress in the silicon substrates on the leakage current, a buried P-N junction was used. The buried P-N junction has less sensitivity to SiO2/Si interface states which could dominate the leakage current, and is applied to low leakage devices. We quantified the magnitude of the mechanical stress utilizing Raman spectroscopy and examined the process parameter to reduce the leakage current.
{"title":"Influence of STI stress on leakage current in buried P-N junction","authors":"T. Tomimatsu, T. Yamaguchi, M. Mizuo, T. Yamashita, Y. Kawasaki, A. Ishii","doi":"10.1109/IWJT.2013.6644517","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644517","url":null,"abstract":"Reduction of leakage current is a grand challenge in logic and analog devices from viewpoints of low power consumption, high resolution, low noise, and so on. As for the P-N junction leakage current, it is reported that the leakage current is caused by several factors such as junction depth [1], shallow trench isolation (STI) stress [2], metal contamination, and crystal defects [3]. In this paper, we focused on the influence of the STI stress on the junction leakage current. To clarify the impact of internal stress in the silicon substrates on the leakage current, a buried P-N junction was used. The buried P-N junction has less sensitivity to SiO2/Si interface states which could dominate the leakage current, and is applied to low leakage devices. We quantified the magnitude of the mechanical stress utilizing Raman spectroscopy and examined the process parameter to reduce the leakage current.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117250615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644506
Ikeda Akihiro, K. Nishi, Daichi Marui, H. Ikenoue, T. Asano
In this report, we extend our investigation to characterization of junctions produced by the excimer laser irradiation to 4H-SiC immersed in phosphoric acid.
在本报告中，我们将研究扩展到准分子激光照射浸入磷酸中的4H-SiC所产生的结的表征。
{"title":"Characteristic of pn junction formed in 4H-SiC by using excimer-laser processing in phosphoric solution","authors":"Ikeda Akihiro, K. Nishi, Daichi Marui, H. Ikenoue, T. Asano","doi":"10.1109/IWJT.2013.6644506","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644506","url":null,"abstract":"In this report, we extend our investigation to characterization of junctions produced by the excimer laser irradiation to 4H-SiC immersed in phosphoric acid.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128541079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644518
Hsueh-Liang Huang, Jyi-Tsong Lin, Chen-Chi Tsai, Kuan-Yu Chen, Y. Lu, S. Hsu, Po-Hsieh Lin
This paper presents a new CMOS inverter (CGTFET), which is composed of a Gated control IIP for load transistor (Gated-IIP) and a tunneling field effect transistor (TFET) for driven transistor. Based on the measurement data of Gated-IIP and TFET devices published, we have for the first time drawn the load lines and the quiescent point line (Q line) of the new designed CGTFET compared with the conventional CTFET to verify its feasibility. Additionally, due to our unique structure has simple fabrication process and the output node is shared by the load and the driver, the integration density of our structure can be reduced dramatically. The area benefit thus more than 32.6% has been achieved compared with the conventional CTFET layout. Further, we use Ge Source to further improve NTFET (Q1) driven ability and the performance of the CGTFET.
{"title":"A study of new type CMOS inverter with Gated-IIP load and TFET driver for 22nm technology node","authors":"Hsueh-Liang Huang, Jyi-Tsong Lin, Chen-Chi Tsai, Kuan-Yu Chen, Y. Lu, S. Hsu, Po-Hsieh Lin","doi":"10.1109/IWJT.2013.6644518","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644518","url":null,"abstract":"This paper presents a new CMOS inverter (CGTFET), which is composed of a Gated control IIP for load transistor (Gated-IIP) and a tunneling field effect transistor (TFET) for driven transistor. Based on the measurement data of Gated-IIP and TFET devices published, we have for the first time drawn the load lines and the quiescent point line (Q line) of the new designed CGTFET compared with the conventional CTFET to verify its feasibility. Additionally, due to our unique structure has simple fabrication process and the output node is shared by the load and the driver, the integration density of our structure can be reduced dramatically. The area benefit thus more than 32.6% has been achieved compared with the conventional CTFET layout. Further, we use Ge Source to further improve NTFET (Q1) driven ability and the performance of the CGTFET.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131012960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644496
Y. Sasaki, A. De Keersgieter, Chew Soon Aik, T. Chiarella, G. Hellings, M. Togo, G. Zschatzsch, A. Thean, N. Horiguchi
Extension doping for FinFETs is more difficult compared with planar devices due to fin geometry. An amorphization problem for NMOS FinFETs and photo resist shadowing for CMOS FinFETs are pointed out when standard ion implantation (I/I) is used. Amorphization of the fin results in poor recrystallization during subsequent annealing. The whole fin can easily be amorphized when As is implanted at high dose to form source and drain extensions, especially for narrow FinFETs. Fin sputter erosion can be seen when narrow tilt angle standard As I/I is employed. These are serious concerns because they degrade the device performance and increase the variability. In this study, the improvement of the fin amorphization and the fin sputter erosion of standard I/I is reported. The optimization procedure and the optimized result of standard I/I are discussed. In addition, the difference between the device performance for 7 degrees tilt As I/I and the optimized 30 degrees tilt As I/I, which is almost -conformal doping, has been quantified.
{"title":"Optimization of standard As ion implantation for NMOS Si bulk FinFETs extension","authors":"Y. Sasaki, A. De Keersgieter, Chew Soon Aik, T. Chiarella, G. Hellings, M. Togo, G. Zschatzsch, A. Thean, N. Horiguchi","doi":"10.1109/IWJT.2013.6644496","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644496","url":null,"abstract":"Extension doping for FinFETs is more difficult compared with planar devices due to fin geometry. An amorphization problem for NMOS FinFETs and photo resist shadowing for CMOS FinFETs are pointed out when standard ion implantation (I/I) is used. Amorphization of the fin results in poor recrystallization during subsequent annealing. The whole fin can easily be amorphized when As is implanted at high dose to form source and drain extensions, especially for narrow FinFETs. Fin sputter erosion can be seen when narrow tilt angle standard As I/I is employed. These are serious concerns because they degrade the device performance and increase the variability. In this study, the improvement of the fin amorphization and the fin sputter erosion of standard I/I is reported. The optimization procedure and the optimized result of standard I/I are discussed. In addition, the difference between the device performance for 7 degrees tilt As I/I and the optimized 30 degrees tilt As I/I, which is almost -conformal doping, has been quantified.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131029260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644508
L. Qi, K. Mok, M. Aminian, T. Scholtes, E. Charbon, L. Nanver
In this paper, the reverse biasing and breakdown properties of the PureB diodes are investigated for different methods of processing the PureB anode window and the metal contacting. In particular, micron-sized devices are examined in order to assess their suitability for use in dense imaging arrays that may require operation as avalanche photodiodes to obtain the necessary photosensitivity [6]. For such small devices implanted guard rings cannot be implemented without paying a penalty in fill-factor. At the same time it is also desirable to position the photosensitive area away from the oxide perimeter where permanent damage can be inflicted by high reverse currents. Therefore, a “virtual” guard, using an n-enhancement implantation in the central region of the diode is applied here.
{"title":"Reverse biasing and breakdown behavior of PureB diodes","authors":"L. Qi, K. Mok, M. Aminian, T. Scholtes, E. Charbon, L. Nanver","doi":"10.1109/IWJT.2013.6644508","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644508","url":null,"abstract":"In this paper, the reverse biasing and breakdown properties of the PureB diodes are investigated for different methods of processing the PureB anode window and the metal contacting. In particular, micron-sized devices are examined in order to assess their suitability for use in dense imaging arrays that may require operation as avalanche photodiodes to obtain the necessary photosensitivity [6]. For such small devices implanted guard rings cannot be implemented without paying a penalty in fill-factor. At the same time it is also desirable to position the photosensitive area away from the oxide perimeter where permanent damage can be inflicted by high reverse currents. Therefore, a “virtual” guard, using an n-enhancement implantation in the central region of the diode is applied here.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133361392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644495
R. Duffy, M. Shayesteh, I. Kazadojev, R. Yu
Ideal source and drain regions rely on high dopant solubility in the crystalline substrate, in order to boost activation and reduce sheet resistance, and low dopant diffusivity, to facilitate device scaling. High-concentration doping of Ge can be quite a substantial problem, as it is difficult to activate impurity atoms to a high enough level, prevent them escaping during thermal treatments, while maintaining good crystalline integrity of the semiconductor substrate. With future FET devices fabricated with nanowire, fin, or ultra-thin-body architectures, as reiterated by The International Technology Roadmap for Semiconductors, this problem may be challenging for many years to come. In this paper Ge doping challenges will be reviewed, including our ability to model such materials, as well as looking at potential future solutions.
{"title":"Germanium doping challenges","authors":"R. Duffy, M. Shayesteh, I. Kazadojev, R. Yu","doi":"10.1109/IWJT.2013.6644495","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644495","url":null,"abstract":"Ideal source and drain regions rely on high dopant solubility in the crystalline substrate, in order to boost activation and reduce sheet resistance, and low dopant diffusivity, to facilitate device scaling. High-concentration doping of Ge can be quite a substantial problem, as it is difficult to activate impurity atoms to a high enough level, prevent them escaping during thermal treatments, while maintaining good crystalline integrity of the semiconductor substrate. With future FET devices fabricated with nanowire, fin, or ultra-thin-body architectures, as reiterated by The International Technology Roadmap for Semiconductors, this problem may be challenging for many years to come. In this paper Ge doping challenges will be reviewed, including our ability to model such materials, as well as looking at potential future solutions.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126636125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644497
S. Sakai, N. Hamamoto, Y. Nakashima, H. Onoda
Ion implantation is doping process for manufacturing semiconductor. Doping process contains not only implanting doping atoms at a controlled depth profile but also making damages caused by collisions between ions and silicon crystal atoms, knock-on silicon atoms and silicon crystal atoms. A characteristic of doping atoms such as boron, phosphorous and arsenic is well known because it is easy to measure its resistivity and depth profile. On the other hand it is difficult to measure damages. The damage consist vacancies and interstitials in silicon crystals. We have to measure nothing and same atoms in the same crystal atoms. In order to measure damages characteristics we have to fabricate transistor devices, because damages region after thermal budget is too small to measure.
{"title":"Damage control with cluster ion implantation","authors":"S. Sakai, N. Hamamoto, Y. Nakashima, H. Onoda","doi":"10.1109/IWJT.2013.6644497","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644497","url":null,"abstract":"Ion implantation is doping process for manufacturing semiconductor. Doping process contains not only implanting doping atoms at a controlled depth profile but also making damages caused by collisions between ions and silicon crystal atoms, knock-on silicon atoms and silicon crystal atoms. A characteristic of doping atoms such as boron, phosphorous and arsenic is well known because it is easy to measure its resistivity and depth profile. On the other hand it is difficult to measure damages. The damage consist vacancies and interstitials in silicon crystals. We have to measure nothing and same atoms in the same crystal atoms. In order to measure damages characteristics we have to fabricate transistor devices, because damages region after thermal budget is too small to measure.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125719150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644492
T. Kimoto, K. Kawahara, H. Niwa, T. Okuda, J. Suda
In electric power conversion systems of power infrastructures, electric vehicles, and power supplies, Si-based power semiconductor devices are employed as a key hardware. Reduction of power dissipation in the conversion systems is strongly required for energy saving. In particular, ultrahigh-voltage power converters with high efficiency are essential to realize a stable and highly efficient electric power network by optimizing the use of solar power and wind-generated power in the future. The efficiency of power converters/inverters strongly relies on the performance of power semiconductor devices employed in the power electronic systems. Silicon carbide (SiC) is a newly-emerging wide bandgap semiconductor, by which high-voltage, low-loss power devices can be realized owing to its superior properties [1-3]. The major features of SiC power devices include high-voltage blocking capability, low on-state resistance, fast switching speed, and high-temperature operation.
{"title":"Junction technology in SiC for high-voltage power devices","authors":"T. Kimoto, K. Kawahara, H. Niwa, T. Okuda, J. Suda","doi":"10.1109/IWJT.2013.6644492","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644492","url":null,"abstract":"In electric power conversion systems of power infrastructures, electric vehicles, and power supplies, Si-based power semiconductor devices are employed as a key hardware. Reduction of power dissipation in the conversion systems is strongly required for energy saving. In particular, ultrahigh-voltage power converters with high efficiency are essential to realize a stable and highly efficient electric power network by optimizing the use of solar power and wind-generated power in the future. The efficiency of power converters/inverters strongly relies on the performance of power semiconductor devices employed in the power electronic systems. Silicon carbide (SiC) is a newly-emerging wide bandgap semiconductor, by which high-voltage, low-loss power devices can be realized owing to its superior properties [1-3]. The major features of SiC power devices include high-voltage blocking capability, low on-state resistance, fast switching speed, and high-temperature operation.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133574898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644509
Y. Matsunaga, Siti Rahmah Binti Aid, S. Matsumoto, J. Borland, M. Tanjyo
Ion implantation with medium current implants has been applied for halo implantation. Indium (In) has been used for halo implantation for suppression of short channel effect [1]. Recently, the advantage of cryogenic ion implantation with medium current implanters has been reported [2]. They showed that the cryogenic BF2 implant improved the short channel rolloff characteristics.
{"title":"Characterization of BF2, Ga and in dopants in Si for halo implantation","authors":"Y. Matsunaga, Siti Rahmah Binti Aid, S. Matsumoto, J. Borland, M. Tanjyo","doi":"10.1109/IWJT.2013.6644509","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644509","url":null,"abstract":"Ion implantation with medium current implants has been applied for halo implantation. Indium (In) has been used for halo implantation for suppression of short channel effect [1]. Recently, the advantage of cryogenic ion implantation with medium current implanters has been reported [2]. They showed that the cryogenic BF2 implant improved the short channel rolloff characteristics.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117231389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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