Efficient test length reduction techniques for interposer-based 2.5D ICs

Abstract

Three-dimensional integration is considered a promising solution to cure the challenges of performance, power consumption, quality, and reliability issues. The feature of 2.5D ICs is that the dies are stacked on a passive silicon interposer and the dies communicate with each other by means of TSV-based interconnects and re-Distribution layers (RDL) within the silicon interposer. This paper aims to investigate the efficient post-bond test technique for the 2.5D ICs with silicon interposer. In order to efficiently reuse the functional interconnects as the parallel TAM (test access mechanism) for testing dies, a novel macro-die-based interconnect reuse strategy and its corresponding design-for-test (DFT) architecture are proposed in this paper. The proposed strategy merges several dies to form a macro die and then connected to other dies to form a daisy chain for testing. Experimental results show that the proposed techniques have higher success rates for the required TAM width constraints. Moreover, since we can get wider TAMs, the test length then can be reduced significantly.