A. Nagao, Chiyoshi Yoshioka, T. Kambe, I. Shirakawa
{"title":"A layout approach to monolithic microwave IC","authors":"A. Nagao, Chiyoshi Yoshioka, T. Kambe, I. Shirakawa","doi":"10.1109/ASPDAC.1995.486233","DOIUrl":null,"url":null,"abstract":"A layout approach is attempted dedicatedly for MMICs (monolithic microwave integrated circuits), on which predominant layout elements are transistors, resistors, capacitors, inductors, coplanar waveguides, T junctions, etc., formed by the GaAs fabrication process. The layout issue typical of such MMICs consists essentially in how to realize a single layer placement of different shapes of layout elements under a variety of spacing, orientating, and shaping constraints. Each layout element is modeled to simplify placement tasks subject to different placement constraints, and then a set of the interconnection requirements among elements is represented by a graph, to which a planarization algorithm is effectively applied. As a result of this planarization, a placement procedure is constructed mainly by repeated application of a merging scheme. A number of experimental results are also shown to demonstrate the practicability of the described layout approach.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.1995.486233","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A layout approach is attempted dedicatedly for MMICs (monolithic microwave integrated circuits), on which predominant layout elements are transistors, resistors, capacitors, inductors, coplanar waveguides, T junctions, etc., formed by the GaAs fabrication process. The layout issue typical of such MMICs consists essentially in how to realize a single layer placement of different shapes of layout elements under a variety of spacing, orientating, and shaping constraints. Each layout element is modeled to simplify placement tasks subject to different placement constraints, and then a set of the interconnection requirements among elements is represented by a graph, to which a planarization algorithm is effectively applied. As a result of this planarization, a placement procedure is constructed mainly by repeated application of a merging scheme. A number of experimental results are also shown to demonstrate the practicability of the described layout approach.