Hybrid circuit and algorithmic timing error correction for low-power robust DSP accelerators

Abstract

Datapath accelerators are a key performance enabler for many digital signal processing systems. Razor provides a means to improve the performance and power efficiency of DSP accelerators by minimizing static guardbands. Unlike with Razor CPU implementations, recovery can be achieved without the complexity and intrusiveness of checkpoint and replay schemes. We demonstrate two recovery approaches, (1) a circuit-level technique that makes use of a small time borrowing window to efficiently correct marginal timing errors, and (2) an approximate error correction scheme to minimize error magnitude of large timing errors using an interpolation-based approach. Both techniques are demonstrated in a 65nm CMOS testchip. Measurement results show a 37% improvement in energy efficiency at 1GS/s using Razor, compared to a margined baseline on the same silicon. The proposed error detection and correction system is shown to maintain a 10% margin to account for fast-moving supply voltage noise.