An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOI

Abstract

This paper presents circuit techniques that support on-chip SRAM dynamic reliability management to prevent half-selected cell stability failure due to Bias Temperature Instability (BTI) degradation. The proposed techniques monitor the BTI degradation in SRAM cells through a replica row and adjust the WWL voltage level with the assist of a two-phase write operation, where the WWL voltage level is divided into two phases to maintain the half-selected cell stability with BTI without compromising other circuit parameters. Test chip measurement shows that the half-selected cell stability failure is reduced significantly with the proposed techniques at a 10% area and 3.42% power overheads in 28-nm FDSOI 16kb SRAM.