{"title":"Technology independent boundary scan synthesis (design flow issues)","authors":"M. Robinson","doi":"10.1109/EURDAC.1993.410670","DOIUrl":null,"url":null,"abstract":"A design flow paradigm that integrates technology independent boundary scan synthesis into a chip design methodology is presented. The approach accommodates multiple vendor boundary scan technologies and the requirements of (sometimes non-1149.1-compliant) user specified boundary scan architectures. Boundary scan synthesis is described and design-specific requirements, 1149.1 compliance verification, boundary scan manufacturing test, and interfacing with the board and system test environments are discussed.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"92 8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1993.410670","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
A design flow paradigm that integrates technology independent boundary scan synthesis into a chip design methodology is presented. The approach accommodates multiple vendor boundary scan technologies and the requirements of (sometimes non-1149.1-compliant) user specified boundary scan architectures. Boundary scan synthesis is described and design-specific requirements, 1149.1 compliance verification, boundary scan manufacturing test, and interfacing with the board and system test environments are discussed.<>
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