High performance clock distribution for CMOS ASICs

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56761

S. Boon, S. Butler, R. Byrne, B. Setering, M. Casalanda, A. Scherf

引用次数: 26

Abstract

An effective clock distribution system is presented for high performance CMOS standard cell designs. The system can achieve clock skew of less than 500 ps with phase delay under 4 ns. The system is flexible, multitiered, netlist-specific, compatible with commercial routers, and accurately modeled. Clock tree structure, interconnect constraints, buffer design methodology, netlist-driven placement, localized clock assignment, simulated annealing, layout reintegration, and simulation modeling are discussed

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用于CMOS asic的高性能时钟分布

提出了一种用于高性能CMOS标准单元设计的有效时钟分配系统。该系统可以实现小于500ps的时钟偏差和小于4ns的相位延迟。该系统具有灵活、多层、特定于netlist、与商用路由器兼容以及精确建模的特点。讨论了时钟树结构、互连约束、缓冲区设计方法、网络列表驱动的放置、局部时钟分配、模拟退火、布局整合和仿真建模

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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