Design of a Low-Voltage Instrumentation Amplifier at 1.2 V

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI:10.1109/asid52932.2021.9651684

Jeni Liao, Jianxiong Yang, Kangling, Minjuan Zheng, M. Shiau, Hong-Chong Wu, Ching-Hwa Cheng, Don-Gey Liu

{"title":"Design of a Low-Voltage Instrumentation Amplifier at 1.2 V","authors":"Jeni Liao, Jianxiong Yang, Kangling, Minjuan Zheng, M. Shiau, Hong-Chong Wu, Ching-Hwa Cheng, Don-Gey Liu","doi":"10.1109/asid52932.2021.9651684","DOIUrl":null,"url":null,"abstract":"In this paper, a low-voltage current-mode instrumentation amplifier (IA) will be investigated. The main structure consists of two Operational Floating Current Conveyors (OFCCs) with a high-pass filter, low-pass filter, and the chopping technique to filter out noises. The OFCC was designed to operate in the current mode that can perform all the functions of an operational amplifier in an instrumentation amplifier at low voltages. A single power supply set at 1.2V to reduce the power consumption was designed in our study. Some of the MOSFETs were designed to operate in the subthreshold region to reduce the power of the circuit. And a self-cascode structure was employed to enhance its tracking capability at the output. In our simulation, the TSMC 0.18μm CMOS technology was used for our OFCC. According to the results, the IA can perform to achieve 99 dB for common mode rejection ratio (CMRR) with a 10 kHz bandwidth. It is highly feasible to realize a low-power wearable electronic device with our IA.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/asid52932.2021.9651684","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

Abstract

In this paper, a low-voltage current-mode instrumentation amplifier (IA) will be investigated. The main structure consists of two Operational Floating Current Conveyors (OFCCs) with a high-pass filter, low-pass filter, and the chopping technique to filter out noises. The OFCC was designed to operate in the current mode that can perform all the functions of an operational amplifier in an instrumentation amplifier at low voltages. A single power supply set at 1.2V to reduce the power consumption was designed in our study. Some of the MOSFETs were designed to operate in the subthreshold region to reduce the power of the circuit. And a self-cascode structure was employed to enhance its tracking capability at the output. In our simulation, the TSMC 0.18μm CMOS technology was used for our OFCC. According to the results, the IA can perform to achieve 99 dB for common mode rejection ratio (CMRR) with a 10 kHz bandwidth. It is highly feasible to realize a low-power wearable electronic device with our IA.

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1.2 V低压仪表放大器的设计

本文将研究一种低压电流型仪表放大器(IA)。主要结构由两个可操作浮动电流输送机(ofcc)组成，分别采用高通滤波器、低通滤波器和斩波技术滤除噪声。OFCC被设计为在电流模式下工作，可以在低电压下执行仪表放大器中运算放大器的所有功能。为了降低功耗，我们设计了一个1.2V的单电源。一些mosfet被设计在亚阈值区域工作，以降低电路的功率。采用自级联码结构增强了输出端的跟踪能力。在我们的模拟中，我们的OFCC采用了台积电0.18μm CMOS技术。结果表明，在10khz带宽下，IA的共模抑制比(CMRR)可达到99db。用我们的IA实现低功耗可穿戴电子器件是非常可行的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)

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