A. Pouydebasque, B. Dumont, F. Wacquant, A. Halimaoui, C. Laviron, D. Lenoble, R. El-Farhane, B. Duriez, F. Arnaud, V. Carron, C. Rossato, S. Pokrant, F. Salvetti, A. Dray, F. Boeuf, T. Skotnicki
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引用次数: 3
Abstract
This paper demonstrates that, for NMOS, the use of LSA and smart junction engineering enable to improve dramatically short channel effects (-65% in DIBL at L/sub g/=45 nm due to lower X/sub j/ and DL) and I/sub on//I/sub off/ performance (+7% I/sub on/ at I/sub off/=100 nA//spl mu/m due to steeper sub-threshold slope and reduced poly-depletion) compared to spike annealed N-MOSFETs. These results show the potential advantage of ultra-high temperature and non diffusive annealing such as LSA that may be necessary for the 45 nm technology and below.
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