Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203874
Dongkyu Lee, Sungkweon Back, S. Tavakoli, S. Heo, H. Hwang
In this study, we achieved n/sup +//p ultra-shallow junction with low energy Bi ion-implantation at low temperature RTA and solid phase epitaxial regrowth (SPER) and investigated its structural and electrical characteristics. The shallow junctions (/spl sim/15 nm) at low temperature annealing (600/spl deg/C) and complete crystallization without defects are achieved. More importantly, junctions at low implant temperature fabricated at this low thermal budget can be adequate and tailored for source, drain extensions for high-K dielectric and metal-electrode MOSFET device applications.
{"title":"N/sup +//p ultra-shallow junction with low energy bismuth ion-implantation at low temperature","authors":"Dongkyu Lee, Sungkweon Back, S. Tavakoli, S. Heo, H. Hwang","doi":"10.1109/IWJT.2005.203874","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203874","url":null,"abstract":"In this study, we achieved n/sup +//p ultra-shallow junction with low energy Bi ion-implantation at low temperature RTA and solid phase epitaxial regrowth (SPER) and investigated its structural and electrical characteristics. The shallow junctions (/spl sim/15 nm) at low temperature annealing (600/spl deg/C) and complete crystallization without defects are achieved. More importantly, junctions at low implant temperature fabricated at this low thermal budget can be adequate and tailored for source, drain extensions for high-K dielectric and metal-electrode MOSFET device applications.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127762054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203880
K. Shibahara
In this paper, a new scheme for laser annealing named partial-melt laser annealing (PMLA) is proposed based on the knowledges obtained with heat-assisted laser annealing (HALA) investigation. Its feasibility for 10 nm junction was demonstrated. The obtained sheet resistance indicated sufficient dopant activation by this method.
{"title":"Benefits of heat-assist for laser annealing","authors":"K. Shibahara","doi":"10.1109/IWJT.2005.203880","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203880","url":null,"abstract":"In this paper, a new scheme for laser annealing named partial-melt laser annealing (PMLA) is proposed based on the knowledges obtained with heat-assisted laser annealing (HALA) investigation. Its feasibility for 10 nm junction was demonstrated. The obtained sheet resistance indicated sufficient dopant activation by this method.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121849568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203896
D. Connelly, C. Faulkner, P. Clifton, D. Grupp
A method is presented to use electrostatic coupling from a metal of appropriate effective workfunction, separated from the extension region by a thin insulator, to create a "virtual extension" in doped source/drain (S/D) MOSFETs. This electrostatically induced charge layer allows for lower extension doping and increased underlap between the doped extension and the gate, "sharpening" the carrier profile and improving short-channel device performance. In a typical n-channel MOSFET, switching currents in clock-limiting circuit paths are predicted to be 24% higher.
{"title":"Improved short-channel n-FET performance with virtual extensions","authors":"D. Connelly, C. Faulkner, P. Clifton, D. Grupp","doi":"10.1109/IWJT.2005.203896","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203896","url":null,"abstract":"A method is presented to use electrostatic coupling from a metal of appropriate effective workfunction, separated from the extension region by a thin insulator, to create a \"virtual extension\" in doped source/drain (S/D) MOSFETs. This electrostatically induced charge layer allows for lower extension doping and increased underlap between the doped extension and the gate, \"sharpening\" the carrier profile and improving short-channel device performance. In a typical n-channel MOSFET, switching currents in clock-limiting circuit paths are predicted to be 24% higher.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130247479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203895
D. Grupp, D. Connelly, C. Faulkner, P. Clifton
By imposing an ultra-thin insulator between low-workfunction metals and silicon, the Schottky barrier of the junction can be substantially reduced, reducing junction resistance. With this approach, low Schottky barrier metal S/D MOSFETs with Mg and Yb as S/D metals are demonstrated.
{"title":"A new junction technology for low-resistance contacts and Schottky barrier MOSFETs","authors":"D. Grupp, D. Connelly, C. Faulkner, P. Clifton","doi":"10.1109/IWJT.2005.203895","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203895","url":null,"abstract":"By imposing an ultra-thin insulator between low-workfunction metals and silicon, the Schottky barrier of the junction can be substantially reduced, reducing junction resistance. With this approach, low Schottky barrier metal S/D MOSFETs with Mg and Yb as S/D metals are demonstrated.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133182974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203876
V. Faifer, M. Current, T. Nguyen, T. Wong, V. Souchkov
A powerful new tool for non-contact analysis of sheet resistance and leakage current in p-n junctions, based on junction photo-voltage analysis of carrier recombination, carrier spreading and loss in the junction, has been developed. The method has been demonstrated to be effective in measurements of p-n junctions from /spl sim/10 nm to >1 nm and over a dose range of /spl sim/10/sup 11/ to >10/sup 15/ ions/cm/sup 2/. RsL metrology is the first tool to provide dose metrology coverage over the full depth and dose range of CMOS transistor doping. The stability of the measurement results in an Rs repeatability for all junction conditions and does not require surface preparation, such as oxide strip, prior to measurement. RsL methods provide direct evaluation of junction leakage current, which is especially useful for shallow junction technology evaluation. The RsL probe has been incorporated into a fully-automated tool for in-line pilot line and production process development and production control applications.
{"title":"Non-contact measurement of sheet resistance and leakage current: applications for USJ-SDE/halo junctions","authors":"V. Faifer, M. Current, T. Nguyen, T. Wong, V. Souchkov","doi":"10.1109/IWJT.2005.203876","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203876","url":null,"abstract":"A powerful new tool for non-contact analysis of sheet resistance and leakage current in p-n junctions, based on junction photo-voltage analysis of carrier recombination, carrier spreading and loss in the junction, has been developed. The method has been demonstrated to be effective in measurements of p-n junctions from /spl sim/10 nm to >1 nm and over a dose range of /spl sim/10/sup 11/ to >10/sup 15/ ions/cm/sup 2/. RsL metrology is the first tool to provide dose metrology coverage over the full depth and dose range of CMOS transistor doping. The stability of the measurement results in an Rs repeatability for all junction conditions and does not require surface preparation, such as oxide strip, prior to measurement. RsL methods provide direct evaluation of junction leakage current, which is especially useful for shallow junction technology evaluation. The RsL probe has been incorporated into a fully-automated tool for in-line pilot line and production process development and production control applications.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114610339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203890
S. Zhu, A. Nakajima, Y. Yokoyama, K. Ohkura
The solid-state reaction of nickel and substrate germanium was performed by isochronously annealing at a temperature ranging from 250-600/spl deg/C in vacuum. The reaction has been begun at 250/spl deg/C, and substantial polycrystalline NiGe film has been formed at 350/spl deg/C. The formed NiGe film has an orthorhombic structure with dimensions comparable to that of bulk NiGe. With increasing the annealing temperature from 400 to 600/spl deg/C, the film surface roughness increases due to the increase of the grain size. All nickel germanide/n-Ge Schottky contacts has similar Schottky barrier height around 0.47-0.48 eV due to the Fermi level pinning effect.
{"title":"Temperature dependence of Ni-germanide formed by Ni-Ge solid-state reaction","authors":"S. Zhu, A. Nakajima, Y. Yokoyama, K. Ohkura","doi":"10.1109/IWJT.2005.203890","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203890","url":null,"abstract":"The solid-state reaction of nickel and substrate germanium was performed by isochronously annealing at a temperature ranging from 250-600/spl deg/C in vacuum. The reaction has been begun at 250/spl deg/C, and substantial polycrystalline NiGe film has been formed at 350/spl deg/C. The formed NiGe film has an orthorhombic structure with dimensions comparable to that of bulk NiGe. With increasing the annealing temperature from 400 to 600/spl deg/C, the film surface roughness increases due to the increase of the grain size. All nickel germanide/n-Ge Schottky contacts has similar Schottky barrier height around 0.47-0.48 eV due to the Fermi level pinning effect.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124967922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203888
H. Sauddin, H. Tamura, K. Okashita, Y. Sasaki, H. Ito, B. Mizuno, K. Kakushima, K. Tsutsui, H. Iwai
Rapid scaling in silicon CMOS devices has forced the junction depth requirement needed for S/D extensions of MOSFET to be as shallow as 10 nm in the next 45 nm technology node [1]. For this reason, the plasma doping method is considered to be promising compared to the conventional ion implantation, since it has significant advantages such as very high throughput and more compact in system hardware [2]-[6]. Formation of ultra-shallow p-type junction using boron is considerably difficult due to low energy requirement on doping and rapid diffusion of boron during thermal annealing that can increase junction depth. Very short time annealing such as flash lamp annealing (FLA) or spike rapid thermal annealing (RTA) is required to form such shallow junctions [7]-[ 10]. Fig. 1 is a plot of the R,-Xj relationship using the combination of the plasma doping and dopant activation process by FLA or spike RTA, which shows a successful formation of ultra-shallow junction [11][ 12]. However, the study on the leakage current across the ultra-shallow junction has been relatively limited. Since the impurity profile, the condition of amorphization, and the defect formation in the silicon wafers doped by the plasma doping are different from those by the conventional ion implantation, the characteristics ofthe residual defects after the activation annealing, to which the electrical characteristics of the junction is sensitive, might be different between the two.
{"title":"Reverse Current of Plasma Doped p+/n Ultra-Shallow Junction","authors":"H. Sauddin, H. Tamura, K. Okashita, Y. Sasaki, H. Ito, B. Mizuno, K. Kakushima, K. Tsutsui, H. Iwai","doi":"10.1109/IWJT.2005.203888","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203888","url":null,"abstract":"Rapid scaling in silicon CMOS devices has forced the junction depth requirement needed for S/D extensions of MOSFET to be as shallow as 10 nm in the next 45 nm technology node [1]. For this reason, the plasma doping method is considered to be promising compared to the conventional ion implantation, since it has significant advantages such as very high throughput and more compact in system hardware [2]-[6]. Formation of ultra-shallow p-type junction using boron is considerably difficult due to low energy requirement on doping and rapid diffusion of boron during thermal annealing that can increase junction depth. Very short time annealing such as flash lamp annealing (FLA) or spike rapid thermal annealing (RTA) is required to form such shallow junctions [7]-[ 10]. Fig. 1 is a plot of the R,-Xj relationship using the combination of the plasma doping and dopant activation process by FLA or spike RTA, which shows a successful formation of ultra-shallow junction [11][ 12]. However, the study on the leakage current across the ultra-shallow junction has been relatively limited. Since the impurity profile, the condition of amorphization, and the defect formation in the silicon wafers doped by the plasma doping are different from those by the conventional ion implantation, the characteristics ofthe residual defects after the activation annealing, to which the electrical characteristics of the junction is sensitive, might be different between the two.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129582752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203891
Soon-Young Oh, J. Yun, Yong-Jin Kim, Won-Jae Lee, A. Tuya, H. Ji, Ui-Sik Kim, Han-Seob Cha, S. Heo, Jeong‐gun Lee, G. Han, Yoo-Jeong Cho, Yeong Cheol Kim, Jin-Suk Wang, H. Lee
In this paper, a novel Ni/Co/Ni/TiN structure to improve the thermal stability of NiSi by forming highly thermal stable ternary phase, i.e., (Co/sub x/Ni/sub 1-x/)Si/sub 2/ especially at the top region of NiSi is proposed. The Ni/Co/Ni/TiN structure is very promising for the nanoscale MOSFET technology which needs the ultra shallow junction and high temperature post silicidation processes.
{"title":"Ni/Co/Ni/TiN structure for highly thermal immune NiSi for CMOSFETs application","authors":"Soon-Young Oh, J. Yun, Yong-Jin Kim, Won-Jae Lee, A. Tuya, H. Ji, Ui-Sik Kim, Han-Seob Cha, S. Heo, Jeong‐gun Lee, G. Han, Yoo-Jeong Cho, Yeong Cheol Kim, Jin-Suk Wang, H. Lee","doi":"10.1109/IWJT.2005.203891","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203891","url":null,"abstract":"In this paper, a novel Ni/Co/Ni/TiN structure to improve the thermal stability of NiSi by forming highly thermal stable ternary phase, i.e., (Co/sub x/Ni/sub 1-x/)Si/sub 2/ especially at the top region of NiSi is proposed. The Ni/Co/Ni/TiN structure is very promising for the nanoscale MOSFET technology which needs the ultra shallow junction and high temperature post silicidation processes.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114542715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203878
S. Abo, S. Ichihara, T. Lohner, J. Gyulai, F. Wakaya, M. Takai
Ultra shallow arsenic profiles implanted into Si with an energy range from 0.5 to 3 keV to a dose of 8/spl times/10/sup 14/ ions/cm/sup 2/ before and after spike annealing were measured by medium energy ion scattering (MEIS) with a toroidal electrostatic analyzer (TEA). A shift of the peak of arsenic profile to the surface after spike annealing was observed by MEIS measurement. Most of the implanted arsenic atoms were trapped in the native oxide layer after spike annealing.
{"title":"Ultra shallow As profiling before and after spike annealing using medium energy ion scattering","authors":"S. Abo, S. Ichihara, T. Lohner, J. Gyulai, F. Wakaya, M. Takai","doi":"10.1109/IWJT.2005.203878","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203878","url":null,"abstract":"Ultra shallow arsenic profiles implanted into Si with an energy range from 0.5 to 3 keV to a dose of 8/spl times/10/sup 14/ ions/cm/sup 2/ before and after spike annealing were measured by medium energy ion scattering (MEIS) with a toroidal electrostatic analyzer (TEA). A shift of the peak of arsenic profile to the surface after spike annealing was observed by MEIS measurement. Most of the implanted arsenic atoms were trapped in the native oxide layer after spike annealing.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124182612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203883
H. Kamiyanagi, S. Shibata
In this paper, the correlation between the charging phenomena and the photo-resists material after medium dose implantation is reported. To investigate the characteristic change of the photo-resist after ion implantation, the photo-resist removal performance is studied by FT-IR and SEM cross-section image analysis. The result shows that carbonization of photo-resist is promoted by the ion implantation. Both i-line photo-resist and KrF photo-resist were studied. The Si wafer was covered by the 400nm SiO/sub 2/ film. The surface potential measurement results of photoresist coating on SiO/sub 2/ film for various implantations were investigated. The results suggest that the destruction of the finer device due to charging at medium dose implantation will occur more frequently as the resolution of photo-resist is improved by lowering the bonding energy.
{"title":"Charging phenomena of the medium dose implantation by a carbonization of the surface layer of the photo-resist","authors":"H. Kamiyanagi, S. Shibata","doi":"10.1109/IWJT.2005.203883","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203883","url":null,"abstract":"In this paper, the correlation between the charging phenomena and the photo-resists material after medium dose implantation is reported. To investigate the characteristic change of the photo-resist after ion implantation, the photo-resist removal performance is studied by FT-IR and SEM cross-section image analysis. The result shows that carbonization of photo-resist is promoted by the ion implantation. Both i-line photo-resist and KrF photo-resist were studied. The Si wafer was covered by the 400nm SiO/sub 2/ film. The surface potential measurement results of photoresist coating on SiO/sub 2/ film for various implantations were investigated. The results suggest that the destruction of the finer device due to charging at medium dose implantation will occur more frequently as the resolution of photo-resist is improved by lowering the bonding energy.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116302344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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