Dopant redistribution and loss during ternary silicide Co/sub x/Ni/sub 1-x/Si/sub 2/ formation

Abstract

As CMOS devices are scaled to sub-100 nm region, dopant loss during silicide anneal becomes a critical issue. Reducing the thermal budget for silicide anneal is desirable to minimize the dopant loss from source/drain and polysilicon gate. With ternary silicide Co/sub x/Ni/sub 1-x/Si/sub 2/, a relatively low anneal temperature can be used to achieve the disilicide phase with a comparable resistance value to CoSi/sub 2/. In this report, the sheet resistance of Co/sub x/N/sub 1-x/Si/sub 2/ (x=1-0.5) at different anneal temperatures has been studied. The dopant redistribution and loss during Co/sub x/Ni/sub 1-x/Si/sub 2/ formation were characterized by secondary ion mass spectrometry (SIMS). In addition, the phase structures of Co/sub x/Ni/sub 1-x/Si/sub 2/ formed were also compared by X-ray diffraction (XRD). The results indicate that an optimal silicide process with low thermal budget can be achieved in ternary silicide Co/sub x/Ni/sub 1-x/Si/sub 2/ structures to reduce dopant loss at source/drain junctions and poly gate, while keeping silicide resistance low.