An 8.5pJ/bit Ultra-Low Power Wake-Up Receiver Using Schottky Diodes for IoT Applications

Mahmoud R. Elhebeary, Li-Yang Chen, S. Pamarti, C. Yang
{"title":"An 8.5pJ/bit Ultra-Low Power Wake-Up Receiver Using Schottky Diodes for IoT Applications","authors":"Mahmoud R. Elhebeary, Li-Yang Chen, S. Pamarti, C. Yang","doi":"10.1109/ESSCIRC.2019.8902825","DOIUrl":null,"url":null,"abstract":"In this paper, we present an always-on ultra-low power (ULP) wake-up receiver (WuRx) that constantly listens to the channel. We propose a two-phase WuRx architecture resulting in a 12% reduction in the average power consumption compared to conventional single-phase architectures. The first phase detects the existence of a signal and triggers the second phase responsible for signature detection. A CMOS integrable Schottky diode is proposed for power detection utilizing passive gain from impedance matching network. In the second phase, we propose a novel, low power data-locked startable oscillator to correlate the received data with predefined signature, which avoids the use of power-hungry crystal oscillator and features 1nW/kHz efficiency. The proposed system operates at 750MHz and achieves a low wake-up latency of 200µs, a -50dBm sensitivity at a data rate of 200 kbps, a 1.69 µW average power and achieves a FOM~8.5pJ/bit. The system is implemented in 65nm CMOS technology and occupies an area of 1mm×0.75mm.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2019.8902825","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

Abstract

In this paper, we present an always-on ultra-low power (ULP) wake-up receiver (WuRx) that constantly listens to the channel. We propose a two-phase WuRx architecture resulting in a 12% reduction in the average power consumption compared to conventional single-phase architectures. The first phase detects the existence of a signal and triggers the second phase responsible for signature detection. A CMOS integrable Schottky diode is proposed for power detection utilizing passive gain from impedance matching network. In the second phase, we propose a novel, low power data-locked startable oscillator to correlate the received data with predefined signature, which avoids the use of power-hungry crystal oscillator and features 1nW/kHz efficiency. The proposed system operates at 750MHz and achieves a low wake-up latency of 200µs, a -50dBm sensitivity at a data rate of 200 kbps, a 1.69 µW average power and achieves a FOM~8.5pJ/bit. The system is implemented in 65nm CMOS technology and occupies an area of 1mm×0.75mm.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
基于肖特基二极管的8.5pJ/bit超低功耗唤醒接收器
在本文中,我们提出了一种持续监听信道的超低功耗(ULP)唤醒接收器(WuRx)。我们提出了一种两相WuRx架构,与传统的单相架构相比,平均功耗降低了12%。第一阶段检测信号的存在并触发负责签名检测的第二阶段。提出了一种利用阻抗匹配网络无源增益进行功率检测的CMOS可积肖特基二极管。在第二阶段,我们提出了一种新颖的低功耗数据锁定可启动振荡器,将接收到的数据与预定义签名相关联,从而避免了耗电晶体振荡器的使用,并具有1nW/kHz的效率。该系统工作频率为750MHz,唤醒延迟低至200µs,数据速率为200kbps时灵敏度为-50dBm,平均功率为1.69µW, FOM为8.5pJ/bit。该系统采用65nm CMOS技术,占地面积为1mm×0.75mm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO An Integrated Programmable High-Voltage Bipolar Pulser With Embedded Transmit/Receive Switch for Miniature Ultrasound Probes Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR An 18 dBm 155-180 GHz SiGe Power Amplifier Using a 4-Way T-Junction Combining Network A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1