SET Fault Tolerant Combinational Circuits Based on Majority Logic

Abstract

This work proposes the use of analog majority gates to implement combinational circuits that are intrinsically tolerant to transient faults. We propose a new type of voter circuit that uses some knowledge from the analog design arena, and show that these circuits can be used to implement fully fault tolerant modules, in a more efficient way than using triple modular redundancy (TMR). Second, based on already known techniques used to implement any combinational function with the use of majority gates, it is proven that a semi-analog voter can be used to implement fault tolerant majority gates that perform the same functions as the regular combinations of AND, OR and INVERTER gates. Finally, the implementation and test of an adder circuit, using both conventional TMR and the proposed solution, is described and analyzed, in order to confirm that the proposed solution is fault tolerant and also compares favorably to some classic designs that are not 100 percent fault tolerant