Standardizable and automated procedures to measure and simulate very complex 3D packaging parasitics with highest accuracy, shown for a TSOP50 as example

Abstract

The recent development of computing speeds for u-processors and memory, reaching cycle times which correspond to data transfer rates between 400 Mbits/(sec*pin) to 1 GHz/(sec*pin), requires precise and automated procedures, allowing to simulate the complex packaging parasitics of complete packages with experimental accuracy. With the used TSOP50 example it is demonstrated, how the needed automated simulation procedures can be implemented. The simulated results were verified by standardizable experimental procedures. The methodology is capable of describing complete PCBs including the components with layout precision.