Characterization of FinFET SRAM cells with asymmetrically gate underlapped bitline access transistors under process parameter fluctuations

Abstract

Two new six-FinFET memory circuits with asymmetrically gate underlapped bitline access transistors are evaluated in this paper under process parameter fluctuations. The strengths of the asymmetrical bitline access transistors are weakened during read operations and enhanced during write operations as the direction of current flow is reversed. The average read static noise margin of the statistical samples with the asymmetrical memory cells is up to 75.8% higher as compared to the standard symmetrical six-FinFET SRAM cell under process parameter fluctuations. Furthermore, the average leakage power consumption with the asymmetrical memory cells is reduced by up to 19% as compared to the standard symmetrical six-FinFET SRAM cell under process variations in a 15nm FinFET technology.