Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks

Abstract

A novel 8T SRAM bitcell is proposed for computing dot-products using current-mode accumulation. A write disturb issue has been eliminated by adding two extra transistors into a standard 6T SRAM bitcell. Besides, we embed a column ADC in each column-based neuron to address the ADC overhead issue of conventional analog compute-in-memory macros. The resolution of ADC is reconfigurable from 1 to 5bit. A test-chip is fabricated using 65nm, and the energy-efficiency of bitwise operation is 490-to-15.8TOPS/W at 1-5bit.