Optimization of Low Temperature PECVD Dielectric Stacks foR Via Reveal Passivation

Abstract

Advanced packaging technologies, incorporating through-silicon vias (TSVs) have the potential to improve functionality and electrical performance of semiconductor devices in a reduced package size. Such technologies are coming to prominence for devices requiring high bandwidth memory in emerging applications such as self-driving cars, machine learning and real-time speech processing [1]–[3]. In ‘via-middle’ process flows, the TSVs are exposed from the back side of the wafer by grind and plasma etch steps. Dielectric layers deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD) serve to passivate and mechanically support the exposed TSV prior to bump/RDL formation and then chip-to-wafer or wafer-to-wafer bonding. Prior to via reveal processing, device wafers are bonded to silicon or glass carriers and thinned to around 50μm. The temporary bonding material imposes a temperature constraint of ~190°C during all subsequent via reveal process steps. This temperature constraint is especially challenging for the PECVD passivation processes where films with stable electrical and mechanical properties are required. Controlling PECVD film stress is also critical as stresses can cause excessive wafer bow in thinned wafers unless countermeasures are taken. While average stress must be controlled, it is also critical to minimize within-wafer stress as this will impact die-level bow and affect subsequent die-attach processes. In this paper, we report on silicon nitride (SiN) - silicon oxide (SiO) stacks deposited at <190°C which give excellent electrical properties with leakage current densities < 1E-9 A.cm-2 and breakdown voltages >10 MV.cm-1. These films are also optimized in terms of step coverage and stress characteristics. Crucially, electrical properties and stack stress are shown to be stable with no moisture absorption or drift in film properties over time when exposed to atmosphere.