Wen-Ye Liu, Tianxiang Wu, Tianyang Yan, Fan Yang, Yong Chen, Shunli Ma
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引用次数: 0
Abstract
This paper reports the analysis and design of a 26-38GHz balanced frequency doubler. The balanced frequency doubler eliminates odd harmonics by using the characteristics of the circuit. We employ a cascade of two-stage amplifiers to increase output power, and a transformer-based magnetic-coupled resonator (MCR) matching technique to widen the bandwidth. Besides, the transformer can realize the single-ended to differential conversion without penalizing additional power consumption. The frequency doubler is designed in a 0.15 µm GaAs pHEMT process. Post-layout simulation results show that the output power is greater than 10dBm over 26-38GHz, and the fundamental-to-harmonic suppression is greater than 15 dBc. The DC power consumption is 23 mA at a 5-V supply. The chip area is 0.75×1.55 mm2.
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