P. Coudrain, J. Colonna, C. Aumont, G. Garnier, P. Chausse, R. Segaud, K. Vial, A. Jouve, T. Mourier, T. Magis, P. Besson, L. Gabette, C. Brunet-Manquat, N. Allouti, C. Laviron, S. Chéramy, E. Saugier, J. Pruvost, A. Farcy, N. Hotellier
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引用次数: 25
Abstract
This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.
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