Examination of LOCOS process parameters and the measurement of effective width

Abstract

Device isolation by means of LOCOS and field implantation are commonly incorporated in current MOS processes. These two process steps interact to affect the effective MOS transistor width. The authors examine the topographical features determined by pad oxide and nitride thicknesses and compare the physical with the effective electrical width. It is concluded that the limit in topographical packing density may be achieved by physical reduction of the bird's beak, but for varying pad oxide/nitride mask combinations the effective device width is limited by the presence of the field implant.<>