Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161716
R. Vollertsen, W. Kleppmann
Problems arising from the use of a test structure area that is too small or too large when performing dielectric reliability investigations of DRAMs (dynamic random-access memories) are pointed out. The authors discuss the applicability of different models for the transformation of measured t/sub bd/ distributions to larger areas and demonstrate the feasibility of the mathematical combination of subareas within the same chip to a larger area. An optimum test structure for dielectric reliability engineering for the phase of technology development is deduced.<>
{"title":"Dependence of dielectric time to breakdown distributions on test structure area","authors":"R. Vollertsen, W. Kleppmann","doi":"10.1109/ICMTS.1990.161716","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161716","url":null,"abstract":"Problems arising from the use of a test structure area that is too small or too large when performing dielectric reliability investigations of DRAMs (dynamic random-access memories) are pointed out. The authors discuss the applicability of different models for the transformation of measured t/sub bd/ distributions to larger areas and demonstrate the feasibility of the mathematical combination of subareas within the same chip to a larger area. An optimum test structure for dielectric reliability engineering for the phase of technology development is deduced.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126619222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161725
Y. Kuroki, S. Hasegawa, T. Honda, Y. Iida
An X-ray exposure mask was evaluated using electrical test structures. Linewidth was calculated from van der Pauw sheet resistivity and four-terminal bridge resistance. The four-terminal bridge gave a high resolution of 0.002 mu for 0.6- mu m patterns. It was confirmed that the electrical measurement has very high accuracy and reproducibility. A misalignment vector map was demonstrated by a pair o four-terminal bridges. The van der Pauw resistor was also applied for reducing batting error in electron-beam lithography.<>
{"title":"X-ray exposure mask accuracy evaluation using electrical test structures","authors":"Y. Kuroki, S. Hasegawa, T. Honda, Y. Iida","doi":"10.1109/ICMTS.1990.161725","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161725","url":null,"abstract":"An X-ray exposure mask was evaluated using electrical test structures. Linewidth was calculated from van der Pauw sheet resistivity and four-terminal bridge resistance. The four-terminal bridge gave a high resolution of 0.002 mu for 0.6- mu m patterns. It was confirmed that the electrical measurement has very high accuracy and reproducibility. A misalignment vector map was demonstrated by a pair o four-terminal bridges. The van der Pauw resistor was also applied for reducing batting error in electron-beam lithography.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124331092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161749
N. Koike, M. Ito, H. Kuriyama
A technique for wafer level parallel testing of hot-carrier lifetime has been developed. Transistors of the same dimensions were adjacently arranged on the same chip, and the lifetimes were extrapolated from their measured lifetime at a low drain voltage for practical use. This technique was applied to the optimization of LDD (lightly doped drain) sidewall thickness. This technique eliminates the disturbance of the hot-carrier lifetime extrapolation caused by nonuniformity of the hot-carrier lifetimes on a wafer, and makes possible optimization of process parameters in a short period of time.<>
{"title":"A hot carrier parallel testing technique to give a reliable extrapolation","authors":"N. Koike, M. Ito, H. Kuriyama","doi":"10.1109/ICMTS.1990.161749","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161749","url":null,"abstract":"A technique for wafer level parallel testing of hot-carrier lifetime has been developed. Transistors of the same dimensions were adjacently arranged on the same chip, and the lifetimes were extrapolated from their measured lifetime at a low drain voltage for practical use. This technique was applied to the optimization of LDD (lightly doped drain) sidewall thickness. This technique eliminates the disturbance of the hot-carrier lifetime extrapolation caused by nonuniformity of the hot-carrier lifetimes on a wafer, and makes possible optimization of process parameters in a short period of time.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124483362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161743
J. A. Power, A. Mathewson, W. Lane
A methodology for the generation of MOSFET device model parameter sets which reflect measured device performance variations is described and assessed for its accuracy and suitability in predicting actual circuit variations. The proposed scheme is based on the principal component method of multivariate statistical techniques and utilizes Monte Carlo simulations. Comparisons between the predictions of device and circuit characteristics and measured characteristics over a wafer lot are shown and discussed. It is suggested that the techniques used are most suitable for the prediction of the measured distributions of precision analog circuits rather than large digital circuits where 25 or more circuit simulations may be totally unacceptable because of the amount of CPU time required.<>
{"title":"MOSFET statistical parameter extraction using multivariate statistics","authors":"J. A. Power, A. Mathewson, W. Lane","doi":"10.1109/ICMTS.1990.161743","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161743","url":null,"abstract":"A methodology for the generation of MOSFET device model parameter sets which reflect measured device performance variations is described and assessed for its accuracy and suitability in predicting actual circuit variations. The proposed scheme is based on the principal component method of multivariate statistical techniques and utilizes Monte Carlo simulations. Comparisons between the predictions of device and circuit characteristics and measured characteristics over a wafer lot are shown and discussed. It is suggested that the techniques used are most suitable for the prediction of the measured distributions of precision analog circuits rather than large digital circuits where 25 or more circuit simulations may be totally unacceptable because of the amount of CPU time required.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115752140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161752
T. Wada, I. Matsuo, T. Umemoto
Results of a study of electromigration at interconnect vias with respect to lifetime of the vias are presented. It is shown that the dependence of the lifetime of the vias on current and on temperature as well as the effect of copper doping is similar to that found in the aluminum stripe. The lifetime is nearly inversely proportional to the number of vias in a chain and the failure occurs in random vias. It is also found that lifetime is affected both by the number of vias and by the total metal length. The lifetime depends on the size of the vias.<>
{"title":"Study of electromigration at interconnect vias","authors":"T. Wada, I. Matsuo, T. Umemoto","doi":"10.1109/ICMTS.1990.161752","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161752","url":null,"abstract":"Results of a study of electromigration at interconnect vias with respect to lifetime of the vias are presented. It is shown that the dependence of the lifetime of the vias on current and on temperature as well as the effect of copper doping is similar to that found in the aluminum stripe. The lifetime is nearly inversely proportional to the number of vias in a chain and the failure occurs in random vias. It is also found that lifetime is affected both by the number of vias and by the total metal length. The lifetime depends on the size of the vias.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128856462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161729
D. Khera, L. W. Linholm, R. A. Allen, M. Cresswell, V.C. Tyree, W. Hansford, C. Pina
The authors describe an approach for evaluating and refining the rules, based on test structure measurements, to be entered into the knowledge base of an expert system that characterizes device performance. The objective is to qualify the performance of rules determined by a machine-learning classification application with the best knowledge available from the human experts. The technique combines a machine-learning approach with the traditional heuristic-based development of an expert system. Strengths and weaknesses of the individual techniques are compared.<>
{"title":"Knowledge verification of machine-learning procedures based on test structure measurements","authors":"D. Khera, L. W. Linholm, R. A. Allen, M. Cresswell, V.C. Tyree, W. Hansford, C. Pina","doi":"10.1109/ICMTS.1990.161729","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161729","url":null,"abstract":"The authors describe an approach for evaluating and refining the rules, based on test structure measurements, to be entered into the knowledge base of an expert system that characterizes device performance. The objective is to qualify the performance of rules determined by a machine-learning classification application with the best knowledge available from the human experts. The technique combines a machine-learning approach with the traditional heuristic-based development of an expert system. Strengths and weaknesses of the individual techniques are compared.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123625971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161707
A. Walton, M. Fallon, J. Stevenson, A. Ross, R. Holwill
The contact area is an important parameter in the measurement of specific sheet resistivity. The authors propose models which can be used to represent the area of contact together with the measurements that are required for the calculation of contact area. Particular attention is given to optical measurements, SEM (scanning electron microscope), and Vernier-type measurements.<>
{"title":"A methodology for evaluating the area of contacts to improve the accuracy of contact resistance measurements","authors":"A. Walton, M. Fallon, J. Stevenson, A. Ross, R. Holwill","doi":"10.1109/ICMTS.1990.161707","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161707","url":null,"abstract":"The contact area is an important parameter in the measurement of specific sheet resistivity. The authors propose models which can be used to represent the area of contact together with the measurements that are required for the calculation of contact area. Particular attention is given to optical measurements, SEM (scanning electron microscope), and Vernier-type measurements.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"586 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123135029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161718
J. Kumagai, S. Sawada, K. Toita
A measurement technique was developed that makes it possible to estimate both trap charges and the center of the trap-charge distribution, the so-called charge centroid. This technique is applicable to the study of trap/detrap characteristics of injected charges in the gate insulator film of a stacked capacitor with a heavily doped polysilicon/insulator/heavily doped polysilicon structure. C-V characteristics for the stacked capacitor are modeled by using depletion layers in both polysilicon electrodes. Experimental fitting of the model to C-V data was carried out and trap charges and the charge centroid were obtained. Using this technique, trap/detrap characteristics for nanometer-think ONO film were investigated, and the deterioration in DRAM (dynamic random-access memory) cell signal voltage for a stacked capacitor cell, due to detrapping the trap charges, is discussed.<>
{"title":"Novel measurement technique for trapped charge centroid in gate insulator (of DRAM)","authors":"J. Kumagai, S. Sawada, K. Toita","doi":"10.1109/ICMTS.1990.161718","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161718","url":null,"abstract":"A measurement technique was developed that makes it possible to estimate both trap charges and the center of the trap-charge distribution, the so-called charge centroid. This technique is applicable to the study of trap/detrap characteristics of injected charges in the gate insulator film of a stacked capacitor with a heavily doped polysilicon/insulator/heavily doped polysilicon structure. C-V characteristics for the stacked capacitor are modeled by using depletion layers in both polysilicon electrodes. Experimental fitting of the model to C-V data was carried out and trap charges and the charge centroid were obtained. Using this technique, trap/detrap characteristics for nanometer-think ONO film were investigated, and the deterioration in DRAM (dynamic random-access memory) cell signal voltage for a stacked capacitor cell, due to detrapping the trap charges, is discussed.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123885016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161741
E. Mazaleyrat, D. Céli, A. Juge, B. Cialdella
The recent development of BiCMOS and advanced bipolar and merged bipolar CMOS and DMOS technologies requires the enhancement of both models and parameter extraction strategies for the bipolar device. In order to take into account special behavior such as the base push-out effect or the nonideal base current, new features have been added to the classical SPICE BJT (bipolar junction transistor) model. A flexible software tool has been developed to allow the use of different parameter extraction schemes suitable for a wide range of device behaviors. Experimental validations have been performed in DC analysis. The RMS (root mean square) error on current gain is less than 2%.<>
{"title":"A new bipolar extraction tool for wide range of device behaviours","authors":"E. Mazaleyrat, D. Céli, A. Juge, B. Cialdella","doi":"10.1109/ICMTS.1990.161741","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161741","url":null,"abstract":"The recent development of BiCMOS and advanced bipolar and merged bipolar CMOS and DMOS technologies requires the enhancement of both models and parameter extraction strategies for the bipolar device. In order to take into account special behavior such as the base push-out effect or the nonideal base current, new features have been added to the classical SPICE BJT (bipolar junction transistor) model. A flexible software tool has been developed to allow the use of different parameter extraction schemes suitable for a wide range of device behaviors. Experimental validations have been performed in DC analysis. The RMS (root mean square) error on current gain is less than 2%.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134065057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161747
H. Momose, T. Maeda, K. Inoue, Y. Urakawa, K. Maeguchi
A novel test structure was used to evaluate a latchup phenomenon in a bipolar and MOSFET merged device for the BiNMOS gate. Its characteristics were analyzed by varying the test pattern. In the latchup measurement, a MOS current was used to trigger the device, with setting the normal n-p-n bipolar transistor active. As a result, it was revealed that this parasitic phenomenon is associated with a parasitic bipolar transistor below the MOSFET gate, and it was verified that the parasitic collector resistance is the main cause of the parasitic bipolar turn on. In addition, a longer-channel MOSFET is helpful but not sufficient to form a latchup-free state. Consequently, it was confirmed that the test structures and measurement method provide an experimental basis for the latchup-free state.<>
{"title":"Novel test structures for the characterization of latch-up tolerance in a bipolar and MOSFET merged device","authors":"H. Momose, T. Maeda, K. Inoue, Y. Urakawa, K. Maeguchi","doi":"10.1109/ICMTS.1990.161747","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161747","url":null,"abstract":"A novel test structure was used to evaluate a latchup phenomenon in a bipolar and MOSFET merged device for the BiNMOS gate. Its characteristics were analyzed by varying the test pattern. In the latchup measurement, a MOS current was used to trigger the device, with setting the normal n-p-n bipolar transistor active. As a result, it was revealed that this parasitic phenomenon is associated with a parasitic bipolar transistor below the MOSFET gate, and it was verified that the parasitic collector resistance is the main cause of the parasitic bipolar turn on. In addition, a longer-channel MOSFET is helpful but not sufficient to form a latchup-free state. Consequently, it was confirmed that the test structures and measurement method provide an experimental basis for the latchup-free state.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121669267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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