Modeling of real bistables in VHDL

Abstract

A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modeled as a basic structure, orienting its implementation towards its inclusion in a cell library. Two applications are included: a description of a more complex latch (D-type) and a description of a circuit containing three latches where metastable signals are propagated. Simulation results show that the presented model provides very realistic information about the device behavior, which until now had to be obtained through electric simulation.<>