0.16 mW, 7–70 GHz distributed power detector with 75 dB voltage sensitivity in 130 nm standard CMOS technology

Abstract

This paper presents the design and implementation of a low power, wideband and high sensitivity CMOS power detector in 130 nm standard CMOS technology. It utilises a travelling-wave structure to achieve wideband input matching bandwidth from 7 GHz to more than 70 GHz. By biasing the power detectors in subthreshold regime, it achieves a measured peak voltage sensitivity of 75 dB at 7 GHz while maintaining more than 67 dB from 100 MHz up to 70 GHz. The DC power consumption of the proposed design is 0.156 mW from 1.2 V supply. The total area of the power detector is 380 μm × 180 μm, excluding pads.