Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits

Abstract

Based on reliability simulation and reliability hotspot identification with simulator ARET, a concept of local design-for-reliability is proposed and a detailed redesign algorithm has been developed for CMOS digital circuits under device degradation mechanisms, such as hot-carrier and gate oxide wear-out. This algorithm improves circuit overall reliability by modifying channel length of hotspot gate and channel widths of some other gates around hotspot iteratively. By performing local redesign for reliability, circuit reliability can be significantly improved, while the originally designed overall circuit performance is still maintained.